Electronics

Resistor (R):    limits current flow, Ohm's law V = IR
                 Units: Ohms (Ω), kΩ, MΩ
                 Color code: Brown-Black-Red = 1-0-×100 = 1 kΩ

Capacitor (C):   stores charge, blocks DC, passes AC
                 Units: Farads (F), typically µF, nF, pF
                 Time constant: τ = RC
                 Charging: V(t) = V_max × (1 - e^(-t/RC))

Inductor (L):    stores energy in magnetic field, opposes current change
                 Units: Henries (H), typically mH, µH
                 Opposes changes in current (like inertia)

Diode:       one-way valve for current (forward ≈ 0.7V drop for silicon)
             LED: light-emitting diode, 1.8-3.3V forward
             Zener: voltage regulator (reverse breakdown)

Transistor:  electronic switch / amplifier
  BJT:       current-controlled (Base-Collector-Emitter)
             NPN: small base current → large collector current
  MOSFET:    voltage-controlled (Gate-Source-Drain)
             Used in CPUs — billions per chip
             Logic gate building block

Op-Amp:     differential amplifier, very high gain
            Inverting: V_out = -(R2/R1) × V_in
            Non-inverting: V_out = (1 + R2/R1) × V_in

Gate     Symbol   Truth (A,B→Out)     Transistors
──────────────────────────────────────────────────
NOT      ─▷o─    0→1, 1→0             2 (1 CMOS pair)
AND      ─D─     11→1, else 0         6
OR       ─)─     00→0, else 1         6
NAND     ─Do─    11→0, else 1         4 (universal)
NOR      ─)o─    00→1, else 0         4 (universal)
XOR      ─)=─    same→0, diff→1       8-12

NAND is universal: any logic function can be built from NAND gates alone
NOT = NAND(A, A)
AND = NAND(NAND(A,B), NAND(A,B))
OR  = NAND(NAND(A,A), NAND(B,B))

Half adder:    A + B → Sum(A⊕B), Carry(A∧B)
Full adder:    A + B + Cin → Sum, Cout
  Sum = A ⊕ B ⊕ Cin
  Cout = (A∧B) ∨ (Cin∧(A⊕B))

Multiplexer:   select one of N inputs based on select lines
  2-to-1 MUX:  Out = (¬S∧A) ∨ (S∧B)

Decoder:       n inputs → 2^n outputs (only one active)
  Address decoder in memory: select which chip/bank

Flip-flop:    stores 1 bit, changes on clock edge
  SR:         Set/Reset
  D:          Data (output follows input on clock)
  JK:         Universal (toggle, set, reset, hold)
  T:          Toggle

Register:     group of flip-flops (8-bit, 16-bit, 64-bit)
Counter:      increments on each clock pulse
Clock:        oscillator providing timing signal
  CPU clock: 3.5 GHz = 3.5 × 10^9 cycles/sec
  Period: 1/3.5GHz ≈ 0.286 nanoseconds per cycle

┌──────────────────────┐
│        CPU           │
│  ┌──────┐ ┌───────┐  │
│  │ ALU  │ │Control│  │
│  │      │ │ Unit  │  │
│  └──────┘ └───────┘  │
│  ┌──────────────────┐ │
│  │   Registers      │ │
│  └──────────────────┘ │
└──────────┬───────────┘
           │ Bus (address + data)
┌──────────┴───────────┐
│      Memory          │
│  (code + data mixed) │
└──────────────────────┘

Fetch-Decode-Execute cycle:
  1. Fetch instruction from memory at PC address
  2. Decode instruction (what operation, what operands)
  3. Execute (ALU computes, memory read/write)
  4. Increment PC

Level        Size      Latency      Cost/byte
──────────────────────────────────────────────
Registers    ~1 KB     <1 ns        highest
L1 Cache     32-64 KB  ~1 ns        very high
L2 Cache     256-512K  ~3-5 ns      high
L3 Cache     8-64 MB   ~10-20 ns    medium
RAM          16-128 GB ~50-100 ns   low
SSD          1-4 TB    ~100 µs      very low
HDD          4-20 TB   ~5-10 ms     lowest

Each level: ~10× slower, ~10× larger, ~10× cheaper
Cache hit: data found in cache (fast)
Cache miss: must go to slower level (slow)

CMOS dynamic power:  P = α × C × V^2 × f
  α = activity factor (how often gates switch)
  C = capacitance
  V = supply voltage
  f = clock frequency

Key insight: power scales with V^2
  Reducing voltage from 1.2V to 1.0V:
  Power ratio = (1.0/1.2)^2 = 0.69 → 31% reduction

TDP (Thermal Design Power):
  Maximum sustained power a cooling solution must handle
  CPU: 65-125W typical desktop
  Server: 200-350W
  Mobile: 15-45W